Table 6-13: Motorola Dragonball Interface Without Dtack Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f Bus Clock frequency
CLKO
T Bus Clock period
CLKO
t1 Clock pulse width high
t2 Clock pulse width low
A[16:1] setup 1st CLKO when CSX = 0 and
t3
either UWE/LWE or OE = 0
t4 A[16:1] hold from CSX rising edge
CSX asserted for MCLK = BCLK
t5a (CPU wait state register should be programmed
to 4 wait states)
CSX asserted for MCLK = BCLK ÷ 2
t5b (CPU wait state register should be programmed
to 6 wait states)
CSX asserted for MCLK = BCLK ÷ 3
t5c (CPU wait state register should be programmed
to 10 wait states)
CSX asserted for MCLK = BCLK ÷ 4
t5d (CPU wait state register should be programmed
to 12 wait states)
t6 CSX setup to CLKO rising edge
t7 CSX rising edge setup to CLKO rising edge
t8 UWE/LWE setup to CLKO rising edge
t9 UWE/LWE rising edge to CSX rising edge
t10 OE setup to CLKO rising edge
t11 OE hold from CSX rising edge
D[15:0] setup to 3rd CLKO after CSX, UWE/LWE
t12
asserted (write cycle) (see note 2)
CSX rising edge to D[15:0] output Hi-Z (write
t13
cycle)
t14 Falling edge of OE to D[15:0] driven (read cycle)
1st CLKO rising edge after OE and CSX
t15a asserted low to D[15:0] valid for MCLK = BCLK
(read cycle)
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK ÷
t15b
2 (read cycle)
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK ÷
t15c
3 (read cycle)
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK ÷
t15d
4 (read cycle)
CLKO rising edge to D[15:0] output Hi-Z
t16
(read cycle)
1. The MC68EZ328 cannot support the MCLK = BCLK ÷ 3 and MCLK = BCLK ÷ 4 settings without DTACK.
2. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-13: Motorola DragonBall Interface without DTACK Timing

Parameter
MC68EZ328
2.0V 3.3V
Min Max Min Max
16 16
1/f 1/f
CLKO CLKO
28.1 28.1
28.1 28.1
0 0
0 0
8 8
11 11
— —
Note 1 Note 1
— —
Note 1 Note 1
0 0
0 0
1 0
0 0
1 1
0 0
1 0
0 0
4 30 3 15
5.5T 5.5T
CLKO
+ 4 + 20
8T + 8.5T
CLKO
19 + 20
9.5T 10.5T
CLKO
+ 17 + 20
13T 14.5T
CLKO
+ 9 + 20
4 21 2 12
MC68VZ328
2.0V 3.3V
Min Max Min
20
1/f 1/f
CLKO CLKO
22.5 13.6
22.5 13.6
0 0
0 0
8
11
13
17
0 0
0 0
1 0
0 0
1 1
0 0
1 0
0 0
4 30 3
5.5T
CLKO CLKO
+ 4
8T +
CLKO CLKO
19
9.5T
CLKO CLKO
+ 17
13T
CLKO CLKO
+ 9
4 21 2
X31B-A-001-08
Page 53
Unit
Max
33 MHz
ns
ns
ns
ns
ns
8 T
CLKO
11 T
CLKO
13 T
CLKO
17 T
CLKO
ns
ns
ns
ns
ns
ns
ns
ns
15 ns
5.5T
CLKO
ns
+ 20
8.5T
CLKO ns
+ 20
10.5T
CLKO ns
+ 20
14.5T
CLKO ns
+ 20
12 ns
S1D13706